Korean SMEs Shift Focus to NVIDIA and TSMC to Capture AI Chip Opportunities

Global tech giants like NVIDIA and TSMC are advancing their technologies to maintain leadership in the artificial intelligence (AI) industry. Meanwhile, South Korea's small and medium-sized semiconductor enterprises are pivoting toward NVIDIA and TSMC, aligning their efforts with next-generation product development and mass production.

According to reports, Korean SMEs are actively developing and producing new materials to support the introduction of NVIDIA and TSMC’s next-generation technologies. NVIDIA is reportedly planning to unveil its next-generation B300 AI chip in 2025, which is expected to be the most powerful product under NVIDIA's Blackwell architecture. The development of this chip requires new materials and equipment, prompting Korean SMEs to closely monitor progress.

The B300 AI chip is expected to feature a 12-layer stacked HBM3E (High Bandwidth Memory) design and will be manufactured in an on-board configuration. This design integrates high-performance GPUs, HBM, and other chips onto a main substrate. Previously, the connection interface for GPUs was typically installed separately rather than integrated into a substrate. If the new AI chips transition to a substrate-based manufacturing model, the legacy connection interfaces could present performance challenges. As a result, ensuring stable connections between the GPU and the substrate is considered a critical bottleneck to overcome.

NVIDIA’s connection interfaces are primarily supplied by backend processing component companies in South Korea and Taiwan. These companies began testing new connection interface products in Q4 2024, with full-scale production expected to commence by mid-2025. Shipments are anticipated to gradually increase thereafter.

NVIDIA’s key partner, TSMC, is also upgrading its advanced CoWoS (Chip-on-Wafer-on-Substrate) packaging technology. CoWoS places semiconductor chips horizontally on a silicon interposer within the substrate. For its latest HBM products, TSMC is utilizing a smaller interposer, known as CoWoS-L. This evolution has introduced changes in circuit testing, with CoWoS-L requiring circuit widths to shrink from over 2 microns to approximately 1 micron due to increased integration.

To address these requirements, CoWoS circuit measurements are conducted using 3D optical inspection. However, as circuit widths decrease to 1 micron, performance limitations make traditional optical measurements more challenging. To overcome this, TSMC has adopted Atomic Force Microscopy (AFM) for CoWoS inspections. Korean equipment companies have also provided multiple AFM systems to support these experimental efforts.

AFM operates by placing a probe on the atomic surface of a sample, leveraging interactions between the probe and the surface to inspect semiconductor materials. Although slower than optical methods, AFM enables highly precise measurements. If TSMC adopts AFM for CoWoS packaging, this technology could expand its applications to advanced packaging processes, presenting significant opportunities for equipment manufacturers.