Mentor and AMD collaborate with ecosystem partners Microsoft Azure and TSMC to validate the large-si
AMD engineers used Mentor, a TSMC-certified CalibrenmDRC software platform from aSiemensbusiness to complete the physical verification of its largest 7nm chip design, the RadeonInstinctVega20, in about 10 hours. This verification process is performed on the Microsoft Azure cloud platform by using the HB series virtual machine driven by the AMDEPYC processor.
Although AMD's chip design has an impressive 13.2 billion transistors, AMD successfully completed two verifications in 19 hours with the TSMC7nm Calibre design kit running in Azure, dramatically reducing the overall turnaround of physical verification. time. In addition, AMD has extended CalibrenmDRC to 4,140 cores on 69 HB virtual machines, enabling engineers to balance tight deadlines with demanding resource requirements and other costs.
Mentor's new extensions and memory consumption enhancements designed for Calibre software customers have laid the foundation for this milestone achieved through Azure. These features not only help customers reduce memory requirements and associated costs, they can also help significantly reduce the runtime of physical verification when using traditional internal private "fog" or cloud-based configurations. Mentor worked with TSMC and AMD to implement these enhancements and use the latest version of CalibrenmDRC to verify optimization results.
"AMD has requirements for speed and execution quality in the design of cutting-edge semiconductors. Therefore, two verifications through the cloud in one day are critical to the future of the design," said Daniel Bounds, senior director of product marketing at AMD. AMD is pleased to see that Mentor's CalibrenmDRC is available on cloud-based AMDEPYC servers and can be extended from the traditional usage model to the Azure public cloud."
Calibre's latest enhancements enable multiple customers to reduce memory requirements for cloud and legacy configurations by up to 50% when fully chip-proven for the latest 7nm designs. Memory requirements are a key cost driver for public cloud and fog computing, and Calibre has been an industry leader in efficient use of memory.
“Mentor continues to enhance our software solutions to help them accelerate time to market, regardless of where they choose to perform physical verification,” said Joe Sawicki, Executive Vice President, MentorICEDA. “We are pleased to further collaborate with TSMC to provide more Options to help common customers running on third-party clouds leverage TSMC process technology and the Mentor software platform to enable them to fabricate integrated circuits faster through TSMC's new process."
TSMC recently certified Mentor's Calibre tool, which runs on TSMC's 5nm FinFET process node through cloud processes hosted by Microsoft Azure and other leading cloud service providers. Mentor was also invited to join TSMC's OIP Cloud Alliance, which is committed to broadening TSMC's OIP ecosystem with new cloud-ready design solutions and helping customers unlock their innovation potential with TSMC process nodes.
“This latest achievement once again demonstrates Mentor's value to the TSMCOIP ecosystem,” said SukLee, Senior Director, TSMC Design Infrastructure Management. “This collaboration has yielded satisfactory results. We have successfully implemented TSMC's process technology and The design implementation is combined with the Mentor design platform and Microsoft Azure cloud services, which is a significant milestone."
Although AMD's chip design has an impressive 13.2 billion transistors, AMD successfully completed two verifications in 19 hours with the TSMC7nm Calibre design kit running in Azure, dramatically reducing the overall turnaround of physical verification. time. In addition, AMD has extended CalibrenmDRC to 4,140 cores on 69 HB virtual machines, enabling engineers to balance tight deadlines with demanding resource requirements and other costs.
Mentor's new extensions and memory consumption enhancements designed for Calibre software customers have laid the foundation for this milestone achieved through Azure. These features not only help customers reduce memory requirements and associated costs, they can also help significantly reduce the runtime of physical verification when using traditional internal private "fog" or cloud-based configurations. Mentor worked with TSMC and AMD to implement these enhancements and use the latest version of CalibrenmDRC to verify optimization results.
"AMD has requirements for speed and execution quality in the design of cutting-edge semiconductors. Therefore, two verifications through the cloud in one day are critical to the future of the design," said Daniel Bounds, senior director of product marketing at AMD. AMD is pleased to see that Mentor's CalibrenmDRC is available on cloud-based AMDEPYC servers and can be extended from the traditional usage model to the Azure public cloud."
Calibre's latest enhancements enable multiple customers to reduce memory requirements for cloud and legacy configurations by up to 50% when fully chip-proven for the latest 7nm designs. Memory requirements are a key cost driver for public cloud and fog computing, and Calibre has been an industry leader in efficient use of memory.
“Mentor continues to enhance our software solutions to help them accelerate time to market, regardless of where they choose to perform physical verification,” said Joe Sawicki, Executive Vice President, MentorICEDA. “We are pleased to further collaborate with TSMC to provide more Options to help common customers running on third-party clouds leverage TSMC process technology and the Mentor software platform to enable them to fabricate integrated circuits faster through TSMC's new process."
TSMC recently certified Mentor's Calibre tool, which runs on TSMC's 5nm FinFET process node through cloud processes hosted by Microsoft Azure and other leading cloud service providers. Mentor was also invited to join TSMC's OIP Cloud Alliance, which is committed to broadening TSMC's OIP ecosystem with new cloud-ready design solutions and helping customers unlock their innovation potential with TSMC process nodes.
“This latest achievement once again demonstrates Mentor's value to the TSMCOIP ecosystem,” said SukLee, Senior Director, TSMC Design Infrastructure Management. “This collaboration has yielded satisfactory results. We have successfully implemented TSMC's process technology and The design implementation is combined with the Mentor design platform and Microsoft Azure cloud services, which is a significant milestone."