7 nano is so popular! TSMC and Arm jointly launched the first small chip system
On the 26th, TSMC held the Open Innovation Platform Forum in Santa Clara, USA, and jointly presented the industry's first 7-nm chiplet system using TSMC's advanced CoWoS packaging solution and silicon-proven verification, together with the high-performance computing IP factory Arm. Built-in Arm multi-core processor.
TSMC pointed out that this concept-validated small-chip system successfully demonstrated the system-on-a-chip (SoC) key technology that combines the 7nm FinFET process and the 4GHz Arm core to achieve high-performance computing. The product was completed in December 2018. The design was finalized and was successfully produced in April this year.
Drew Henry, senior vice president and general manager of the infrastructure division, said that the latest conceptual verification collaboration with our long-time partner, TSMC, combines TSMC's innovative advanced packaging technology with the flexibility and scalability of the Arm architecture. A well-prepared infrastructure SoC solution will lay the foundation for the future.
Hou Yongqing, deputy general manager of TSMC's technology development, pointed out that this display chip shows that we provide customers with excellent system integration capabilities. TSMC's CoWoS advanced packaging technology and LIPINCON interconnect interface can help customers spread large-size multi-core designs to smaller small ones. Chipsets to provide superior yield and economics. And stressed that this collaboration has further innovated high-performance SoC design for infrastructure applications from cloud to edge computing.
Unlike traditional SoCs where each component of the integrated system is placed on a single die, TSMC spreads the large multi-core design to a smaller chiplet design to better support today's high-performance computing processors. In addition, an efficient design approach allows features to be spread across individual tiny dies produced in different process technologies, providing flexibility, better yield, and lower cost.
It is understood that this small chip system is built on the CoWoS interposer, consisting of two 7nm small chips, each small chip contains four Arm Cortex-A72 processors and one chip built-in cross-core mesh interconnect. The bus, the interchip interconnect has a power efficiency of 0.56pJ/bit, a bandwidth density of 1.6Tb/s/mm2, a 0.3V LIPINCON interface speed of 8GT/s and a bandwidth rate of 320GB/s.
It is worth noting that the 7-nanometer process used in the small-chip system is booming in the second half of the year. IC Insights, the research and development organization, estimates that the revenue of the 7-nanometer process in the fourth quarter of TSMC is expected to reach 33%, driving revenue in the second half of the year. In the first half of the year, it increased by 32%, and foreign capital has also raised its target price. Good news spurred TSMC to hit NT$272.5 in Taiwan in early trading on the 27th, and set a new high price in history. It pushed up the market value to break through the 7 trillion yuan mark, reaching 7.06 trillion yuan. .
TSMC pointed out that this concept-validated small-chip system successfully demonstrated the system-on-a-chip (SoC) key technology that combines the 7nm FinFET process and the 4GHz Arm core to achieve high-performance computing. The product was completed in December 2018. The design was finalized and was successfully produced in April this year.
Drew Henry, senior vice president and general manager of the infrastructure division, said that the latest conceptual verification collaboration with our long-time partner, TSMC, combines TSMC's innovative advanced packaging technology with the flexibility and scalability of the Arm architecture. A well-prepared infrastructure SoC solution will lay the foundation for the future.
Hou Yongqing, deputy general manager of TSMC's technology development, pointed out that this display chip shows that we provide customers with excellent system integration capabilities. TSMC's CoWoS advanced packaging technology and LIPINCON interconnect interface can help customers spread large-size multi-core designs to smaller small ones. Chipsets to provide superior yield and economics. And stressed that this collaboration has further innovated high-performance SoC design for infrastructure applications from cloud to edge computing.
Unlike traditional SoCs where each component of the integrated system is placed on a single die, TSMC spreads the large multi-core design to a smaller chiplet design to better support today's high-performance computing processors. In addition, an efficient design approach allows features to be spread across individual tiny dies produced in different process technologies, providing flexibility, better yield, and lower cost.
It is understood that this small chip system is built on the CoWoS interposer, consisting of two 7nm small chips, each small chip contains four Arm Cortex-A72 processors and one chip built-in cross-core mesh interconnect. The bus, the interchip interconnect has a power efficiency of 0.56pJ/bit, a bandwidth density of 1.6Tb/s/mm2, a 0.3V LIPINCON interface speed of 8GT/s and a bandwidth rate of 320GB/s.
It is worth noting that the 7-nanometer process used in the small-chip system is booming in the second half of the year. IC Insights, the research and development organization, estimates that the revenue of the 7-nanometer process in the fourth quarter of TSMC is expected to reach 33%, driving revenue in the second half of the year. In the first half of the year, it increased by 32%, and foreign capital has also raised its target price. Good news spurred TSMC to hit NT$272.5 in Taiwan in early trading on the 27th, and set a new high price in history. It pushed up the market value to break through the 7 trillion yuan mark, reaching 7.06 trillion yuan. .