The high-speed CMOS DDR synchronous DRAM is vetted with Insignis’ proprietary extended test flow to mitigate against early life failures, ensuring premium quality and long-term reliability for industrial use. It has a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a bank activate command which is then followed by a read or write command.
The device provides programmable read or write burst lengths of 2, 4, or 8. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either auto or self-refresh, are easy to use. In addition, 512 Mb DDR SDRAM features a programmable DLL option.
By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well-suited for applications requiring high memory bandwidth, resulting in a device particularly well-suited to high-performance main memory and graphics applications.
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